The disclosure generally relates to static random-access memory and, in particular, a local evaluation circuit for a static random-access memory.
Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates SRAM from dynamic random-access memory (DRAM), which must be periodically refreshed. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the SRAM is not powered. Typically, each bit in an SRAM is stored on four transistors that form a storage cell having two cross-coupled inverters. The storage cell has two stable states that are denoted ‘0’ and ‘1’. Usually, two additional access transistors serve to control access to the storage cell during read and/or write operations. In general, an SRAM utilizes six metal-oxide semiconductor field-effect transistors (MOSFETs) to store each memory bit. Other types of SRAM chips may use eight or more transistors per bit to facilitate the implementation of more than one port (i.e., read and/or write ports) for use in certain types of video memory and register files.
Generally, the fewer and smaller sized transistors implemented per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and packing more bits on a wafer usually reduces the cost per bit of memory. Access to a typical SRAM cell is facilitated by one or more wordlines that control two access transistors which, in turn, control whether the cell is coupled to one or more bitlines. The wordlines are used to access a cell for both read and write operations. Although it is not strictly necessary to have two bitlines (bitline true (BLT) and bitline complement (BLC)) to read a cell, a data signal and its inverse are typically provided during a read in order to improve noise margins. During read accesses, the bitlines are actively driven high and low by inverters in the SRAM cell. This usually improves SRAM bandwidth, as compared to DRAMs, i.e., in a DRAM a bitline is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards.
The symmetric structure of SRAMs also allows for differential signaling, which makes small voltage swings more easily detectable. Another difference between SRAM and DRAM that contributes to making SRAM faster is that SRAM chips typically accept all address bits at a single time. In contrast, DRAMs typically employ address multiplexing with higher address bits followed by lower address bits over the same package pins in order to reduce DRAM size and cost. An SRAM cell has three different states: standby, reading, and writing. In a standby state an SRAM is idle. In a reading state data has been requested from the SRAM. In a writing state, contents of the SRAM are updated. If wordlines are not asserted, access transistors disconnect an SRAM cell from bitlines. In this case, the two cross-coupled inverters continue to reinforce each other as long as they are connected to a power supply.
Assuming that the content of a cell is a ‘1’, i.e., BLT is a ‘1’, a read cycle is started by precharging both bitlines (BLT and BLC) to a logical ‘1’, then asserting the wordline or lines to enable both of the access transistors. The stored values are transferred to the bitlines with BLT being left at its precharged value and BLC discharging to a logical ‘0’. If the content of the memory was a ‘0’, the opposite would happen and BLC would be pulled toward ‘1’ and BLT toward ‘0’. A sense amplifier senses a small voltage difference between BLT and BLC to determine whether a ‘1’ or ‘0’ was stored on the cell. The start of a write cycle begins by applying the value to be written to the bitlines. To write a logical zero ‘0’ to an SRAM cell, a logical zero ‘0’ is applied to bitline BLT and a logical one ‘1’ is applied to bitline BLC. A logical one ‘1’ is written to the SRAM cell by inverting the values on the bitlines BLT and BLC. The wordlines (i.e., wordline true (WLT) and wordline complement (WLC)) are then asserted and the value that is to be stored is latched in the SRAM cell. It should be appreciated that the bitline input drivers are designed to be stronger than the relatively weak transistors in the SRAM cell so that the bitline drivers can easily override the previous state of the cross-coupled inverters. In general, correct sizing of the transistors in an SRAM cell is required to ensure proper operation.
High-speed memory design has become increasingly important to the overall performance of processors and data processing systems. In general, bitline sensing is one of the largest contributors to memory latency. For a cache memory, for example, bitline sensing can account for as much as two-thirds of total cache latency.